74HC4040D,653

The 74HC4040D is a 12-stage Binary Ripple Counter with a clock input (CP\), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the high-to-low transition of CP\. A high on MR clears all counter stages and forces all outputs low, independent of the state of CP\. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

• CMOS Input levels
• Complies with JEDEC standard No. 7A

Rakendused

Clock & Timing, Industrial, Consumer Electronics, Computers & Computer Peripherals