V2M-N1SDP-0342A

V2M-N1SDP-0342A is a Neoverse N1 system development platform which is an N1 CPU-based development platform for hardware prototyping, software development, system validation and performance profiling or tuning. N1 SDP platform consists of a hardware board with Neoverse N1 SoC running a complete Armv8.2-A open-source software stack that is available through GitHub and other hosting sites such as Linaro. N1 SoC has been developed using 7nm manufacturing process targeting CPU frequency of 2.6GHz.

• Dual-core, dual-cluster SMP configuration with a total of 4 N1 CPUs
• Internal CMN-600 interconnect operating up to 2GHz
• GIC-600 and MMU-600 for interrupt management and I/O virtualization support
• 2 x 72-bit DMC-620 memory controller for dual channel DDR4 2667MHz memory
• 2 cortex-M7 CPU functioning as SCP and MCP for supporting event logging, power and device management
• CoreSight SoC-400 functional debug and trace capability
• Board expansion support with corresponding external ports
• 1x CCIX Gen4 x16 port, 1x PCIe x16 Gen3 link to 48-lane switch with downstream slots and peripherals
• 32bit MIPI-60 trace port, JTAG debug port plus Arm CoreSight 20 JTAG connector for debug only
• Optional PCIe Gen3 riser card kit to connect 2xN1 SDP board back-to-back over CCIX for SMT operation